Recomienda este artículo a tus amigos:
Low Power Digital CMOS Design Anantha P. Chandrakasan 1995 edition
Low Power Digital CMOS Design
Anantha P. Chandrakasan
Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation.
409 pages, biography