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Real Chip Design and Verification Using Verilog and VHDL Senior Editor and Contributor Ben Cohen
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Real Chip Design and Verification Using Verilog and VHDL
Senior Editor and Contributor Ben Cohen
Real Chip Design and Verification Using Verilog and VHDL addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices, and uses Verilog and VHDL as a tool for expression of the desired architectures. This book is not intended to teach either HDL, as there are several books specifically geared toward teaching the languages. However, it provides various architectural design primitives, applications, and verification techniques, along with design methodologies and common practices.
| Medios de comunicación | Libros Paperback Book (Libro con tapa blanda y lomo encolado) |
| Publicado | 6 de octubre de 2002 |
| ISBN13 | 9781539769712 |
| Editores | Createspace Independent Publishing Platf |
| Páginas | 426 |
| Dimensiones | 216 × 279 × 22 mm · 979 g |
| Lengua | Inglés |