Prudhvi Sai Rangisetti

Partial Reconfigurable Fir Filters Using Dpr: Implementation Using Dynamic Partial Reconfiguration Prudhvi Sai Rangisetti

Reconfigurable hardware might be the next step which will give computer performance a new big leap forward. The idea is to use the, nowadays, high performance FPGA technology to adapt the hardware to the problem. Dynamic partial reconfiguration of FPGA offers new design space with variety of benefits. This Dissertion intends to describe the development of a dynamically reconfigurable system which supports multiple modules running concurrently, all with hardware support. A standard Xilinx FPGA is used to test the possibilities of loading partially new hardware configurations while other parts of the FPGA still are active. An example implementation is also realized in order to exemplify the possibilities within the subject. Its scope is to implement an autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters and flexibility allowing dynamically inserting and/or removing the partial reconfigurable FIR filters with various taps.