Recomienda este artículo a tus amigos:
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test - Frontiers in Electronic Testing Andrei Pavlov Softcover reprint of hardcover 1st ed. 2008 edition
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test - Frontiers in Electronic Testing
Andrei Pavlov
The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
210 pages, biography