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Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs - Analog Circuits and Signal Processing Pedro M. Figueiredo Softcover reprint of hardcover 1st ed. 2009 edition
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs - Analog Circuits and Signal Processing
Pedro M. Figueiredo
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation.
382 pages, biography